LES (LayoutEditor Schematic)
LES is the native file format of the LayoutEditor to store schematics. It also includesg hierarchical components and any other circuit sheets of the SchematicEditor.
Using LES in the LayoutEditor
As LayoutEditor Schematic is the native format the usage is very simple. Just open the schematic with OpenFile from the SchematicEditor. All sheet will be added to the current collection of sheets.
Description of the LES File Format
The LayoutEditor Schematic is a text format in XML style. It has one LayoutEditorSchematic entry which a Sheet sub entry for any sheet. Special chars in names are replaced by its html characters. e.g. space is replaced by &sp;
Example:
<LayoutEditorSchematic>
<Sheet delay>
<Component 48 136 -15 7 0 0 INV openCellLibrary>
devicename=L4
output=X1
</Component>
<Component -40 136 -15 7 0 0 INV openCellLibrary>
devicename=L3
output=X1
</Component>
<Port 142 -6 out>
<Port -294 136 in>
<Wire 0 136 18 136>
<Wire -88 136 -70 136>
<SubComponent delay>
<Description>
created from sheet 'delay'
</Description>
<Parameter>
</Parameter>
<Layout>
[cell]
#condition filename cellname
* . delay
</Layout>
<Prefix sub>
<Label>
delay
</Label>
<Symbol>
<Rect -40 -7 40 7 wire>
<Port -50 0 in>
<Line -50 0 -40 0 wire>
<Text -50 0 wire in>
<Port 50 0 out>
<Line 50 0 40 0 wire>
<Text 40 0 wire out>
<Port 0 -22 VDD global>
<Port 0 -37 VSS global>
</Symbol>
<Netlist hspice>
X$devicename $node(in) $node(out) delay
</Netlist>
<Netlist spectre>
$devicename ( $node(in) $node(out) ) delay
</Netlist>
<Netlist spice>
X$devicename $node(in) $node(out) delay
</Netlist>
<Model hspice>
.subckt delay in out
XL4 VSS VDD Node_1 Node_8 INV_X1
XL3 VSS VDD Node_2 Node_1 INV_X1
XL2 VSS VDD Node_3 Node_2 INV_X1
XL1 VSS VDD in Node_3 INV_X1
XL5 VSS VDD Node_8 Node_5 INV_X1
XL6 VSS VDD Node_5 Node_6 INV_X1
XL7 VSS VDD Node_6 Node_7 INV_X1
XL8 VSS VDD Node_7 Node_13 INV_X1
XL9 VSS VDD Node_10 out INV_X1
XL10 VSS VDD Node_11 Node_10 INV_X1
XL11 VSS VDD Node_12 Node_11 INV_X1
XL12 VSS VDD Node_13 Node_12 INV_X1
.ends delay
</Model>
<Model spectre>
inline subckt delay ( in out )
ends
</Model>
<Model spice>
.subckt delay in out
XL4 VSS VDD Node_1 Node_8 INV_X1
XL3 VSS VDD Node_2 Node_1 INV_X1
XL2 VSS VDD Node_3 Node_2 INV_X1
XL1 VSS VDD in Node_3 INV_X1
XL5 VSS VDD Node_8 Node_5 INV_X1
XL6 VSS VDD Node_5 Node_6 INV_X1
XL7 VSS VDD Node_6 Node_7 INV_X1
XL8 VSS VDD Node_7 Node_13 INV_X1
XL9 VSS VDD Node_10 out INV_X1
XL10 VSS VDD Node_11 Node_10 INV_X1
XL11 VSS VDD Node_12 Node_11 INV_X1
XL12 VSS VDD Node_13 Node_12 INV_X1
.ends delay
</Model>
</SubComponent>
</Sheet>
<Sheet main>
<LabelWire 337 -28 out>
<LabelWire 225 -13 A2>
<LabelWire 4 -43 A1>
<LabelWire -200 140 in>
<Ground -119 36>
<Component -119 140 -16 6 0 0 delay -internal->
devicename=sub1
</Component>
<Component 8 140 -16 6 0 0 delay -internal->
devicename=sub2
</Component>
<Component 228 140 -16 6 0 0 delay -internal->
devicename=sub3
</Component>
<Component -16 64 0 0 270 0 XOR2 openCellLibrary>
devicename=L1
output=X1
</Component>
<Component 205 64 0 0 270 0 XOR2 openCellLibrary>
devicename=L2
output=X1
</Component>
<Component -120 88 0 -11 0 0 supply openCellLibrary>
devicename=p1
</Component>
<Component -200 96 -68 24 90 0 Vac hspice>
devicename=V1
U=1V
Pulse=1V
f=1GHz
Theta=0
Phase=0
</Component>
<Component -272 152 2 -7 0 0 .TRAN hspice>
devicename=TR1
trparameter=10p&sp;10n
</Component>
<Component 120 140 -17 6 0 0 delay -internal->
devicename=sub4
</Component>
<Component 283 -28 0 0 0 0 OR2 openCellLibrary>
devicename=L3
output=X1
</Component>
<Wire -69 140 -42 140>
<Wire -42 140 -42 109 -11 109 -11 82>
<Wire 19 82 19 109 58 109 58 140>
<Wire 178 140 178 109 210 109 210 82>
<Wire 240 82 240 108 278 108 278 140>
<Wire -119 36 -119 56 -119 67 -121 67>
<Wire -200 66 -200 56 -119 56>
<Wire -200 126 -200 140 -169 140>
<Wire 58 140 70 140>
<Wire 170 140 178 140>
<Wire 225 7 225 -13 248 -13>
<Wire 4 7 4 -43 248 -43>
<Wire 323 -28 337 -28 355 -28>
</Sheet>
</LayoutEditorSchematic>