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Alliance

Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC. It is open source and free to use. It was developed in the 90th and is no longer active developed. Especially tools have a graphical user interface are outdated. However it still includes some good command line tools and is the only free open source synthesis tool existing.

Alliance within the LayoutEditor

The digital synthesis and simulation tools of the Alliance CAD System were integrated into the TextEditor which is included in the LayoutEditor. Namely the tools asimut, boom, boog, loon and vasy are used and can be called from the TextEditor on a VHDL file. The VHDL file will be synthesizes and the resulting structual VHDL file can be loaded into the LayoutEditor for a netlist driven layout. The OpenCellLibrary shiped with the LayoutEditor includes any information to do a synthesis for it. Also a digital simulation can be triggered.

(introduced with version 20130525)

SourceCode

The latest existing source code was used and transfered to any platform sopported by the LayoutEditor. No functional modification were done. The modified source code is here.

See also


CategoryTutorial


alliance (last edited 2013-05-25 08:29:05 by dslb-092-077-144-158)